1. Field of the Invention
This invention relates to generating clock signals for electronic devices.
2. Description of the Related Art
Clock synthesizers generate clock signals utilized by a wide variety of electronic products. Referring to FIG. 1, a typical clock synthesizer utilizes a phase-locked loop (PLL) supplied with a reference signal from a source such as a crystal oscillator. The output frequency of the signal supplied by the synthesizer can be determined by a divider value of the feedback divider in the PLL. Thus, a reference frequency supplied to the PLL is multiplied based on the divider value to generate the synthesized clock frequency. For example, feedback divider 118 of PLL 100 may be an integer divider, which divides the reference frequency clock signal by an integer value, N.
FIG. 2A illustrates a PLL 100 with a fractional-N feedback divider 119. In at least one embodiment, DIVIDE RATIO is a digital frequency ratio translated from a code, e.g., a code provided by non-volatile memory (NVM). Sigma-delta modulator 121 supplies a divide sequence to fractional-N feedback divider 119. Fractional-N divider 119 receives a divide value sequence corresponding to the target divider ratio. For example, FIG. 2B illustrates a timing diagram of a divide by 2.25. The input clock (REFCLK) is shown as waveform 201 as having a period of one unit interval (UI). The output of the fractional-N divider, DIVCLK, is shown in waveform 203. As shown in waveform 203, the divide ratio of 2.25 is achieved by a sequence of divide by 2 for three periods and a divide by 3 for one period, assuming a first order sigma-delta modulator is used to control the fractional-N divider. Waveform 205 illustrates the ideal waveform for a divide ratio of 2.25. The quantization noise of the modulator, at the output of the divider 118 is shown as the difference at 207, 209, and 211, between the actual output of the fractional-N divider shown in waveform 203 and the ideal output for a divide by 2.25 shown in waveform 205.
Referring back to FIG. 2A, fractional-N divider 119 supplies the divided signal to phase detector 112 with noise associated with the nature of the fractional-N divider. In fractional-N synthesis, the fractional-N noise may be filtered out by the PLL loop. In addition, phase error correction may be utilized to address the jitter introduced by the divider by introducing an offset into the PLL corresponding to the jitter generated by the fractional-N divider. However, such clock synthesizers may require a complex loop filter and complex voltage-controlled oscillator control that increase the cost in design effort and chip area, resulting in more expensive products that may be too expensive in cost or real estate for significant portions of the clock synthesizer market. Accordingly, low-cost, low-noise, flexible clock synthesizer techniques are desired.